1. Field of the Invention
The present invention relates to a semiconductor device of a hierarchical power source structure having a main power source line and a sub-power source line, and more particularly, to a structure for stabilizing voltage of a sub-power source line.
2. Description of the Background Art
A circuit using CMOS (Complementary MOS) transistors for an integrated circuit is widely known for its low power consumption. A CMOS transistor includes both an N channel MOS transistor (insulated gate type field effect transistor) and a P channel MOS transistor. The current drivability of a CMOS transistor is mainly characterized by the threshold voltage of the MOS transistor, the voltage of the source node, and the voltage applied to the gate. For an N channel MOS transistor, the current drivability is represented by the following equation. EQU Ids=.beta.(Vgs-Vth).sup.2 (1)
where Ids indicates the current across the drain and source of an N channel MOS transistor (drain current), Vgs indicates the gate-source voltage of an MOS transistor, Vth indicates the threshold voltage of an N channel MOS transistor, and .beta. is a constant determined by the ratio of the gate length to the gate width of a MOS transistor. The above equation (1) is satisfied under the operating condition of a saturation region. Here, the saturation region is an operating region that satisfies the following relationship. EQU Vds&gt;Vgs-Vth (2)
where Vds is the drain-source voltage of an N channel MOS transistor. For a P channel MOS transistor, the saturation region is represented by the same expression with a direction of the drain current reversed.
When the power supply voltage is lowered to reduce the power consumption of an integrated circuit, the internal signal within the integrated circuit becomes smaller in amplitude so that the voltage applied to the gate of the MOS transistor is reduced. As a result, the gate-source voltage Vgs becomes lower. Accordingly, drain current Ids becomes smaller from the above equation (1). The output node cannot be charged/discharged at a high speed. Thus the operating speed of the circuit becomes slower.
In order to increase the operating speed with a low power supply voltage under the condition that the size of the gate (ratio of gate width to gate length) of the MOS transistor is identical, the absolute value of the threshold voltage Vth must be reduced. With a smaller absolute value of threshold voltage Vth, a drain current Ids of a magnitude identical to that when the operating power supply voltage is high can be supplied as represented by equation (1). However, there is a problem that power consumption is increased in a non-operating state (standby state) if the absolute value of threshold voltage Vth is reduced.
A small current flows across the source and drain in an MOS transistor even in a non-operating state (even when the gate voltage is at the ground voltage level and N-MOS transistor is off). This slight current is called "sub-threshold current", and is represented by the following equation. EQU Isub=.alpha..multidot.10.sup.(Vgs.spsp.-.sup.Vth)/s :NMOS EQU Isub=.alpha..multidot.10.sup.(Vth.spsp.-.sup.Vgs)/s :PMOS
where S is the parameter referred to as the sub-threshold coefficient (sub-threshold voltage swing) indicating the sub-threshold current characteristic, indicating the level of the gate voltage required to vary drain current Ids by one order of magnitude. Therefore, when only the absolute value of threshold voltage Vth is reduced under the condition of Vgs=0 as in a conventional case, sub-threshold current Isub is increased exponentially. For example, when the absolute value of threshold voltage Vth is reduced by 0.1 V under the condition of S=0.1 V, the sub-threshold leakage current increases by a factor of 10. A hierarchical power supply method is known to reduce this sub-threshold leakage current when an MOS transistor is off.
FIG. 36 schematically shows a structure of a conventional hierarchical power supply. Referring to FIG. 36, the hierarchical power supply includes a main power supply line 1102 coupled to a power supply node for transmitting a power supply voltage Vdd, a sub-power supply line 1103 coupled to main power supply line 1102 through a switching transistor 1100, a main ground line 1104 receiving a ground voltage GND, and a sub-ground line 1105 coupled to main ground line 1104 through a switching element 1101. Switching element 1100 is rendered conductive in response to activation (L level: logical low) of a control signal /SW that determines the activation period of the operation of an internal circuit that utilizes the voltages on power supply lines 1102 and 1103 and ground lines 1104 and 1105. Switching element 1101 is rendered conductive in response to an activation (H level: logical high) of a control signal SW.
In this hierarchical power supply structure, the internal circuit has its source connection determined according to the logic level of the output signal in a standby state (when control signals SW and /SW are inactive, and the MOS transistor forming the internal circuit is off).
In FIG. 36, two logic circuits 1107 and 1108 are shown as typical examples of internal circuits. Logic circuit 1107 includes a p channel MOS transistor 1107a having a source connected to main power supply line 1102, a gate receiving an input signal IN1, and a drain connected to the output node from which an output signal OUT1 is provided, and an n channel MOS transistor 1107b having a source connected to sub-ground line 1105, a gate receiving input signal IN1, and a drain connected to the node from which output signal OUT1 is provided.
Logic circuit 1108 includes a p channel MOS transistor 1108a having a source connected to sub-power supply line 1103, a gate receiving an input signal IN2, and a drain connected to a node from which an output signal OUT2 is provided, and an n channel MOS transistor 1108b having a source connected to main ground line 1104, a gate receiving input signal IN2, and a drain connected to a node from which output signal OUT2 is provided.
According to this connection, logic circuit 1107 provides an output signal OUT1 of an L level in a standby state. Logic circuit 1108 provides an output signal OUT2 of an H level in a standby state. The operation thereof will now be described briefly.
In an operating mode of logic circuits 1107 and 1108, control signals /SW and SW are rendered active. Switching elements 1100 and 1101 conduct, so that main power supply line 1102 is connected to sub-power supply line 1103, and main ground line 1104 is connected to sub-ground line 1105. Therefore, the voltage on sub-power supply line 1103 becomes equal to the level of voltage Vdd on main power supply line 1102. Also, the voltage on sub-ground line 1105 becomes equal to the level of voltage GND on main ground line 1104. Logic circuits 1107 and 1108 carry out a logic process (negate process) according to input signals IN1 and IN2, respectively, to provide output signals OUT1 and OUT2, respectively. MOS transistors 1107a, 1107b, 1108a and 1108b each are a low threshold voltage transistor with the threshold voltage small in absolute value. Operation can be effected at high speed (since the drain current drivability is great) even when power supply voltage Vdd is low.
In a standby state, control signals /SW and SW are inactive. Switching elements 1100 and 1101 do not conduct. Control signal /SW is set to the level of power supply voltage Vdd whereas control signal SW is maintained at the level of the ground voltage. Switching elements 1100 and 1101 are constituted by MOS transistors. The gate-source voltage Vgs is 0 V. Under this state, sub-threshold leakage current flows in each of switching elements 1100 and 1101. Input signals IN1 and IN2 are set to an L level and an H level, respectively. Output signals OUT1 and OUT2 are set at an H level and an L level, respectively.
In logic circuit 1107, the drain-source voltage of MOS transistor 1107a attains the level of 0 V, so that leakage current does not flow. In MOS transistor 1107b, the gate voltage is at the level of the ground voltage, and the drain voltage attains the level of power supply voltage Vdd. Therefore, sub-threshold leakage current flows. In logic circuit 1108, MOS transistor 1108b receives a signal of an H level at its gate. The drain-source voltage is 0 V, so that leakage current does not flow. In contrast, MOS transistor 1108a receives a signal of a power supply voltage level at its gate, so that sub-threshold leakage current flows. By making the sub-threshold leakage current of switching element 1100 smaller than the sub-threshold leakage current of MOS transistor 1108a in logic circuit 1108 (for example, increase the gate width), the voltage level of sub-power supply line 1103 is reduced. The voltage on the line 1103 is settled at a level in which the sub-threshold leakage current supplied by switching element 1100 is in balance with the sub-threshold leakage current of logic circuit 1108 and other internal circuits not shown. Therefore, the voltage of sub-power supply line 1103 becomes lower than the voltage level of main power supply line 1102.
As for sub-ground line 1105, by setting the gate length, for example, such that the sub-threshold leakage current of switching element 1101 becomes smaller than the total sum of the sub-threshold leakage currents of MOS transistor 1107b in logic circuit 1107 and the MOS transistor included in other logic circuits not shown, the voltage level of sub-ground line 1105 is set to a voltage level that provides balance between the sub-threshold leakage current from logic circuit 1107 and other logic circuits not shown and the sub-threshold leakage current discharged through switching element 1101. In this state, the voltage level of sub-ground line 1105 becomes higher than that of ground voltage GND. Therefore, in logic circuit 1107, the source voltage of MOS transistor 1107b becomes higher than the gate voltage. The gate-source voltage Vgs attains the level of a negative voltage for the MOS transistor to be reversely biased deeper to reduce the sub-threshold leakage current. In logic circuit 1108, the source voltage of p channel MOS transistor 1108a becomes lower than the gate voltage thereof. The gate-source voltage attains a positive level for MOS transistor 1108a to be reversely biased deeper. As a result, the sub-threshold leakage current is reduced. It is apparent from the above-described expression of sub-threshold leakage current Isub that the sub-threshold leakage current can be reduced by setting a reverse bias state across the gate and source in comparison to the case where the gate-source voltage Vgs is 0 V.
In logic circuits 1107 and 1108, high speed operation is realized by using a MOS transistor of a low threshold voltage. By changing the voltage level of the sub-power supply line and sub-ground line from the voltage level on the main power supply line and main ground line in the hierarchical power supply structure, the sub-threshold leakage current in a standby state, i.e. the consumed current, can be reduced.
In a standby state as shown in FIG. 37, sub-threshold current Isa supplied from switching element 1100 is set smaller than (equal to when stabilized) sub-threshold leakage current Isb in a standby state of internal circuit 1110 that operates with the voltage on sub-power supply line 1103 used as one operating power supply voltage. When the absolute value of the threshold voltage of switching element 1100 is great and when there are many p channel MOS transistors that flow sub-threshold leakage current in internal circuit 1110, the size of switching element 1100 can be set greater than the size (the ratio of gate width to gate length) of the p channel MOS transistor in internal circuit 1110. However, the ratio of the gate width to the gate length cannot be sufficiently increased (for example, the minimum value of the gate length is limited) since sub-threshold leakage current Isa supplied from switching element 1100 must be set smaller than total sub-threshold leakage current Isb of the entire internal circuit 1110. Therefore, the power consumed by internal circuit 1110 cannot be supplied from main power supply line 1102 to sub-power supply line 1103 at high speed even when switching element 1100 is rendered conductive in a normal operation of internal circuit 1110. The voltage level of sub-power supply line 1103 is reduced, so that internal circuit 1110 cannot operate at high speed.
Even if the ratio of the gate width to the gate length of switching element 1100 is relatively great, the voltage difference between main power supply line 1102 and sub-power supply line 1103 is small. Therefore the drain-source voltage Vds of p channel MOS transistor 1100 is small. Since control signal /SW is driven to the level of the ground voltage when switching element 1100 conducts, switching element 1100 formed of an MOS transistor operates in a non-saturation region. When this drain-source voltage Vds is small, a great drain current cannot be supplied from main power supply line 1102 to sub-power supply line 1103 since the drain voltage is represented by the function of drain-source voltage Vds. There was a problem that reduction in the voltage of sub-power supply line 1103 cannot be compensated for at a high speed. In the transition from a standby state to an operating state, the reduced voltage level of sub-power supply line 1103 can be recovered at high speed to the voltage level of main supply line 1102. Therefore, it is necessary to delay the initiation timing of the operation of internal circuit 1110. Thus, there is a problem that the timing of initiating operation of internal circuit 1110 must be delayed.
When the voltage level of sub-power supply line 1103 is reduced by the operation of internal circuit 1110, the voltage level of sub-power supply line 1103 cannot be recovered at high speed to the original level of power supply voltage Vdd. There is a problem that internal circuit 1110 cannot be operated stably. Particularly, when the voltage level of sub-power supply line 1103 is reduced, the amplitude of the output signal of internal circuit 1110 becomes smaller. The amplitude of the signal applied to the circuit of the next stage becomes smaller, so that the circuit of the next stage cannot be operated at high speed. There is a problem that the operating speed is reduced.
The problem of slow recovery of the voltage drop at sub-power supply line 1103 is also seen in the sub-ground line. In the case of sub-ground line 1105, the voltage level becomes higher than the level of the ground voltage to result in a smaller amplitude of the internal signal. There is a problem that the internal circuit cannot be operated at high speed to charge/discharge the output node.
In a conventional hierarchical power source structure, the main power source line (main power supply line and main ground line) and the sub-power source line (sub-power supply line and sub-ground line) are connected via a switching element. It is therefore difficult to recover the voltage to the original level at high speed during variation of the voltage of the sub-power source line. There is a problem that the internal circuit cannot be operated speedily and stably.